In order to achieve a high-speed and highly-integrated non-volatile memory, a phase-change memory has been developed. The phase-change memory is disclosed in Non-Patent Document 1 (“2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers”, pp. 202 to 203), Patent Document 1 (U.S. Pat. No. 6,487,113), and Patent Document 2 (U.S. Patent Application Publication No. 2004/0151023).
For example, as disclosed in the Non-Patent Document 1, the phase-change memory stores information by using the fact that a phase-change element called a chalcogenide material has a resistance that differs according to its state. Rewriting of the phase-change element is performed by feeding current through the phase-change element for heating. Such a rewrite operation includes those called a reset (RESET) operation and a set (SET) operation. The reset operation is an operation of keeping the phase-change element at a relatively high temperature so that the element is in a high-resistance state (amorphous state). The set operation is an operation of keeping the phase-change element at a relatively low temperature for a sufficient period so that the element is in a low-resistance state (crystalline state). Herein, reading of the phase-change element is performed by feeding current within a range not to change the state of the phase-change element and identifying its high/low resistance.
Also, the Patent Document 1 discloses a method of performing a set operation by first keeping the phase-change element at a relatively high temperature and then subsequently decreasing the temperature in a stepwise manner to a relatively low temperature. Furthermore, the Patent Document 2 describes a system of changing a write condition and a read condition according to an ambient temperature. This Patent Document 2 points out that, because the required set current and reset current are changed according to the ambient temperature, if the set current is fixed at a maximum value, the set current may cause an erroneous reset at some ambient temperature and therefore an operation margin is lost. Moreover, if the reset current is fixed at the maximum value, it is pointed out that an over-reset may occur at some ambient temperature. Still further, it is pointed out that the resistance value in a reset state is changed according to the ambient temperature and thus operation margin at the time of a read determination is lost.
To solve these problems, there is disclosed means in which a chalcogenic resistor same as memory cell materials is used to configure a temperature sensor so that temperature is corrected. That is, this means detects temperature change of a memory cell by a temperature sensor arranged near a memory array and generates a reference voltage reflecting the change, and then this reference voltage is used to generate a set current, a reset current, and a read determination current depending on (inversely proportional to) temperature.
Non-Patent Document 1: “2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers”, pp. 202 to 203
Patent Document 1: U.S. Pat. No. 6,487,113
Patent Document 2: U.S. Patent Application Publication No. 2004/0151023